Reference is made to related applications entitled xe2x80x9cBuffering and Sequencing of Soft Decisions of Multiple Channels Into a Single Shared Biorthogonal Decoderxe2x80x9d, filed on even date herewith Ser. No. 09/239,871; and xe2x80x9cBuffering and Sequencing of Data From Multiple Channels Through a Shared Decoderxe2x80x9d, filed on even date herewith Ser. No. 09/240,171, which applications are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to data receivers and methods of data reception and more particularly to data receivers in satellites and methods of receiving data with satellites which have reduced hardware for demodulating and decoding of data.
2. Description of Prior Art
Channelizers are well known in satellite data reception and function to divide a wide band received signal into a plurality of narrower band signals each of equal bandwidth. The data transmitted on a satellite uplink is typically frequency division multiplexed (FDM) and is divided into sub-bands by channelizers. Depending on the application, the sub-bands are again divided into narrower channels by additional channelizers.
Transmission access is further divided by time division multiplexing (TDM) into slots occupied by a transmission burst. These bursts utilize phase shift keying (usually either BPSK or QPSK) as the modulation method. Typically the bursts have a header that facilitates forming an initial estimate of the carrier phase and a body which carries information typically decoded by means of an error correction code.
Certain functions must be performed to receive data by a satellite which are, separation of the various uplink channels by frequency; the recovery of estimates of the modulated data from the burst body and the passing of the estimates to error correction processing, and the performing of decoding. In some applications, the data content of the burst is encoded in the form of ATM cells which are well known. When encoding utilizes ATM cells, it is necessary to recover the cells from the decoded data and to perform integrity checks upon them.
A satellite data reception system typically has three major sub systems. First, the aforementioned channelizer partitions the frequency spectrum of a beam into sub-bands. A sub-band demodulator and decoder performs demodulation and inner decoding on the signal in each sub-band outputted by the channelizer. A block and cell level processor (block decoder) typically processes the output of each inner decoder to perform outer decoding and cell level functions.
Signals within a sub-band may be arranged into one of three configurations. The sub-band demodulator and inner decoder must have functional capability to process each configuration, which are Type Z where the sub-band signal is configured as twenty-five narrow bandwidth, low data rate channels sharing the bandwidth by FDM; Type Y which is configured for five medium bandwidth channels, again shared by FDM, and Type X which is configured for a single wide bandwidth, high data rate channel occupying the full bandwidth.
In each of the sub-band FDM modes discussed above, transmission may occur in one of two error correction modes which are, ìheavyî or ìlightî. In both the heavy and light cases, an outer code is used for data encoding which is typically a Reed-Solomon code over GF (256) of size (236, 212). In the heavy case, an inner code is also used. This inner code is typically a short rate one-half block code as, for example, the (8,4) biorthogonal code.
Jointly, there are six possible modes of data transmission, which are, XH, XL, YH, YL, ZH, and ZL. In each of these modes, the uplink transmission is organized time wise into frames typically of ninety-three milliseconds where each frame has two portions xc3x1 which are a synch burst portion and a traffic burst portion occupying three and ninety milliseconds respectively. The demodulator inner decoder and data decoder is not required to process the synch burst field. The traffic burst field consists of a number of slots within which individual traffic bursts may be placed by an uplinking earth terminal. Typically, the number of slots in ZH mode is twenty four and in ZL mode is forty eight. In YH and YL modes, there are typically five times as many slots per frame. In XH and XL modes, there are typically twenty five times as many slots per frame. The cumulative encoded data rate is the same in heavy and in light modes in each of the modes X, Y and Z and is typically 0.5, 2.5 and 12.5 megasymbols per second respectively. The demodulator and decoder is required to examine the signal present in each burst slot, demodulate it and decode it regardless of whether it contains a valid traffic burst which is assigned to the uplinking terminal. The demodulator and decoder is required to function reliably with a phase of the uplink signal that is unknown. However, the demodulator and decoder may rely on the signal amplitude being well controlled as a result of uplink power control methods and may rely upon the incoming frequency of both a symbol carrier and the symbol timing being closely aligned to the demodulator and decoder timing. Unlike other burst demodulators, the demodulator and decoder in a satellite relies on the time alignment of the bursts that it is required to process being very precise so that the demodulator and decoder does not need to provide burst continuous delineation for symbol time recovery functions.
Since the ATM protocol requires the cells to be delivered in the same order that they are presented and since usage may involve demultiplexing where more than one channel is used to transport a cell stream, the demodulator and decoder must be sure that all bursts are processed in a predictable order when channelization is used (modes Y and Z) and that burst time order is preserved when heavy and light coding modes are mixed across channels. When the X mode is used, only a single channel is present and all bursts are either in heavy or light mode.
Each of the R decoders and demodulators 10 of the prior art of FIG. 1 receives an input from an X channelizer which provides a sub-band of data which may be divided into five equally spaced Y mode channels or twenty five Z mode channels by a Y and Z channelizer 12. The Y and Z channelizer 12 outputs five channels to a Y time demultiplexer 14 and twenty five channels to a Z time demultiplexer 16.
The direct input from the X channelizer, the five output channels from the Y time demultiplexer and twenty five channels from the Z time demultiplexer are applied to a mode select multiplexer 18 which has a total of twenty five output channels which are identically processed. Only the processing of the first output channel is described herein but it should be understood that the remaining twenty four channels are processed in the same manner with duplicated hardware and processing.
An output channel from the mode select multiplexer 18 is applied to a phase tracking function 20 and a preamble processing function 22 which function together as a phase estimation unit which correlates I and Q samples {p(n)} and {q(n)} against {t(n)} wherein {t(n)} is typically a M length sequence of+ and xe2x88x921""s to produce variables I and Q as follows for light coding:
I=SUM[n=1 to M:p(n)*t(n)] Q=SUM[n=1 to M:q(n)*t(n)]
The phase tracking for heavy burst repeats this operation and sums the two results. The phase tracking function then estimates the initial phase of the burst xcex80 by taking the arctangent of the ratio Q/I:
xcex80=ATN[Q/I].
This correlation action is typically performed in a standard accumulator configured to add or subtract as required by the sign of t(n) and the phase estimate is typically produced using a ROM. The estimate xcex80 of the starting phase is supplied to the phase tracking function 20. The phase estimation provided by the combination of the phase tracking and aforementioned preamble processing functions 20 and 22 provides the estimate xcex8 of the received signal phase in order to provide best bit error rate (BER) performance.
The phase lock loop provided by the phase tracking and preamble processing functions 20 and 22 operates in one of two modes relative to a decision direction depending upon whether the decoder and demodulator 10 is operating in the ZL or ZH modes. For light code bursts, the phase lock loop processes the {p(n)}, {q(n)} sample pairs for each symbol as independent and forms an error estimate for the phase lock loop filter. In a typical case in the light mode, the phase lock loop is a first order phase lock loop which simply accumulates k*xcex5n to yield the phase estimate xcex8 wherein xcex5n is the phase error estimate for each sample pair. Since synchronization for advanced satellites maintains the uplink frequency within a very tight tolerance which is typically no worse than xc2x1500 Hz or equivalently, 0.001 revolution per symbol epoch for the slowest transmission data rate typically 500 kilosymbols per second for the Z mode, a simple first order loop with a gain k in the range of {fraction (1/16)} is adequate to track the phase. The demodulator and decoder may optionally use a lower loop gain when processing bursts from modes Y and X which have a higher symbol rate.
For heavy coded bursts, four consecutive symbols are related which represent a code word in an (8,4) biorthogonal code which is well known. In this case, the decision direction is based on decoded results from the inner decoder 24 which receives the N BIT SOFT DECISIONS output from the phase tracking function 20 containing eight possible bits and outputs the four most likely bits in a manner which is well known. The output of the inner decoder 24 is in the form of a four-bit nibble which is applied to a nibble to byte converter 26 which converts consecutive nibbles from a single channel outputted from the inner decoder 24 into bytes for subsequent processing by outer decoder 28 which may be a Reed-Solomon decoder of well-known construction. The N BIT HARD DECISIONS output from the phase tracking function 20, which is in dibit groups, is applied to a dibit to byte converter 30, which outputs bytes from a single channel for subsequent decoding by the outer decoder 28. The output of the dibit to byte converter 30 is applied to an alignment delay 32 which provides time compensation for the processing delay produced by the inner decoder 24 so that the respective bytes outputted from the soft and hard processing paths become time aligned. The outputs from the nibble to byte converter 26 and the alignment delay 32 are applied to a multiplexer 34 which selects bytes from the soft or the hard decision path for inputting to a descrambler 36 of conventional construction which uses a scrambling code to prevent crosstalk between adjacent beams. The outer decoder 28 typically decodes GF (256) of size (236, 212).
The overall operation of the demodulator and decoder 10 is under the control of the onboard satellite processor (not illustrated) and receives timing signals from the satellite""s uplink timing system which are not described in detail herein in view of their being well known.
The channelizer 10 has its simplest operation in the mode X. In this circumstance, all requisite filtering is performed by the X channelizer which provides the input to the decoder and demodulator 10. In the Y and Z processing modes, the Y and Z channelizer 12 is further required to divide the sub-band output from the X channelizer into further smaller channels for processing as described above.
The processing architecture of each of the output channels from the mode select multiplexer 18 requires substantial hardware for all twenty five Z channels, and is an inefficient decoding architecture for time mulitplexed X channel data streams. This architecture has less efficiency, high complexity, requires more circuitry and consumes substantial DC power which provides reduced processing flexibility for data reception, especially in environments such as satellites. This architecture further requires substantial memory for processing all of the output channels from the mode select multiplexer 18.
The present invention is a receiver and method of receiving data transmissions having a preferred application for reception of data by satellites. The invention buffers and sequences data from multiple channels at selected processing locations in a demodulator and decoder downstream of the output of the phase tracking function which reduces the number of nibble to byte converters, dibit to byte converters and block decoders compared to the prior art. As a result, increased data processing efficiency, better redundancy of processing, reduced consumption of DC power and miniaturization of circuitry is achieved while also providing greater processing flexibility.
A multichannel data demultiplexing and reordering memory processes the output data from multiple channels outputted from the phase tracking function. Time division multiplexed (TDM) processors of multiple channels eliminates parallel processing paths for each of the channels as in the prior art which required a soft and a hard decision processing path for each of the channels.
The invention further is a converter which combines inputs of one or more bits from multiple TDM channels outputted from the phase tracking function into multibit outputs for processing by a single outer decoder. As a result, the parallel processing of the prior art having individual inner decoders for each channel is eliminated. The converter is used in both the TDM multiple channel soft and hard decision processing paths which are outputted from the phase tracking function.
The invention further is a block memory which converts groups of bits from multiple TDM channels into blocks of bits each containing at least one group of bits for sequential decoding by an outer decoder. The block memory eliminates the requirement of an outer decoder in each channel as in the prior art. Outer decoders have sufficient processing speed to sequentially demodulate each of the blocks stored in the block memory which are readout and decoded within the time in the prior art that a single block is decoded.
A receiver in accordance with the invention includes at least one memory, each memory including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal and outputs the stored data samples from a plurality of channels in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and an outer decoder, responsive to data blocks with each data block containing at least one data group, which decodes the data blocks and outputs decoded data blocks. A pair of data processing paths is provided with one of the data processing paths comprising a soft decision data processing path and another of the data processing paths comprising a hard decision data processing path, the pair of data processing paths each containing one of the at least one memory. The soft decision processing path further comprises upstream of one of the at least one memory, another memory including an addressable storage array which stores a sequence of data samples contained in the time division multiplexed signal and outputs the stored data samples in a sequence of the data groups, each data group containing a plurality of samples from one of the plurality of channels and an inner decoder, responsive to the data groups, which decodes the data samples within the data groups and outputs the decoded data samples to the memory in the soft decision processing path. The data samples inputted to the another memory each comprise orthogonally encoded data; and the inner decoder is a biorthogonal decoder. The inner decoder is a Reed-Muller decoder. The receiver is contained in a satellite. The receiver further includes a channelizer, which is responsive to an input bandwidth and which divides the input bandwidth into a plurality of output channels each of equal bandwidth, one of the channels comprising the time division multiplexed signal. The memories each further comprise a write address generator and a read address generator and the addressable storage array contains memory cells which are addressed by addresses generated by the write address generator and the read address generator, the sequence of data samples being written in a group of the memory cells with addresses generated by the write address generator and the sequence of data groups being read out with addresses generated by the read address generator. The another memory further comprises a write address generator and a read address generator and the addressable storage array contains memory cells which are addressed by addresses generated by the write address generator and the read address generator, the sequence of data samples being written in a group of the memory cells of the another memory with addresses generated by the write address generator and the sequence of data groups outputted from a group of memory cells of the another memory with addresses generated by the read address generator.
A method of data reception in accordance with the invention includes storing in at least one memory a received time division multiplexed signal containing a sequence of data samples from a plurality of channels; from the at least one memory outputting the stored data samples in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; decoding with an outer decoder the data samples within data blocks with each data block containing at least one data group; and outputting the decoded data samples of the plurality of data blocks. A pair of data processing paths are provided with one of the data processing paths comprising a soft decision data processing path and another of the data processing paths comprising a hard decision data processing path, and wherein each data processing path contains one of the at least one memory, each memory storing a received time division multiplexed signal containing a sequence of data samples from the plurality of channels, outputting from each memory the stored data samples in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels, decoding the data samples within the data blocks each containing at least one data group, and outputting the decoded data samples. The soft decision path contains another memory, upstream of the memory, which stores a sequence of the data samples and outputs the stored data samples in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; the data group is decoded with an inner decoder; and the data decoded by the inner decoder is outputted to the memory of the soft decision processing. The data samples inputted to the another memory each comprise orthogonally encoded data; and the inner code decoder is a biorthogonal data encoder. The method is performed within a satellite. An input bandwidth is divided with a channelizer into a plurality of output channels each having an equal bandwidth, one of the output channels comprising the time division multiplexed signal. Memory cells of each of the at least one memory are addressed by addresses generated by a read address generator and a write address generator with the sequence of data samples being written in a data group of memory by addresses generated by the write address generator and the sequence of data groups individually outputted from a group of memory cells being generated by addresses generated by the read address generator.